• Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for HBMPHY/DDRPHY/Serdes, Clock trees…
• Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
• Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield.
• Participate in building and enhancing layout flow for faster, higher quality design process.
• Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
• Complete all design quality checks and data quality checks
• Work with Place and Route engineer to integrate analog layouts into top level.
• Do design reviews across global team
• May collaborate in package design (interposer design, RDL design)
• Work closely with design team in Viet Nam, USA and Italy to ensure the success of the whole product.
• May join research programs to implement new ideas for future products and flows
• May lead a layout team to complete a full project
• May mentor junior layout engineers or interns
– Having 4+ years of experience in custom layout.
• Holding BS Degree in Electronics Engineering, Electromechanics, Telecommunications.
• 4+ years of experience in custom layout.
• Familiar with Layout entry tools: Cadence, Synopsys
• Familiar with Layout verification tools: Mentor Calibre, Synopsys ICV
• Understand basic semiconductor fabrication processes
• Understand MOSFET fundamentals
• Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR.
• Experienced with writing layout review presentations and layout verification reports
• Locate in Ho Chi Minh city
• Good English communication
• Good team player
• Self motivated
• Work with highly experienced global team and talented highly motivated Viet Nam engineering team
• Work in a professional, innovative and fun environment.
• Working on most competitive designs such as: High Band Width Memory (HBM) PHY, High Speed PAM4 56G/128G Serdes as well as other designs in a large portfolio of Analog IP such as: High Speed LVDS IO library, Multiple Voltage Domain GPIO, DDR IO Library, ONFI/SD IO library, PLL, DLL, Bandgap Reference, Power Management …
• Opportunity to get in touch with the complete flow of a real complicated Analog Mixed Signal Design: From Specification – RTL/Synthesis – Analog Circuit/Layout – Place & Route – Timing & Physical Sign Off – Packaging – Signal/Power Integrity – Silicon Bring Up.
• Chance to work with the latest possible technology nodes (16nm/14nm/10nm/7nm/5nm) from all foundries.
• Clear career path of self-development to either Technical Expert or Design Leader/Manager
• Travel to USA, Europe and Asia for training or on site support.
Apply here: https://app.jobvite.com/j?cj=oq2f8fwz&s=Vietnamworks