Nanochap is a young fabless semiconductor company headquartered in Hangzhou with the core R&D team in Melbourne, Australia. We specialise in neural interface and biosensing SoCs. The company is committed to the R&D, design, packaging, testing, and commercialisation of ultra-high density neural interface chips, biosensing chips, and other medical device related chips. Nanochap is expanding and we are looking for talents in but not limited to Analog Design, Analog Layout, RTL Design, Physical Design to join our newly opened office in Ho Chi Minh city.
- Responsible for all aspect of physical design from RTL to GDS on sub-micron node, 16nm or lower
- Develop physical design methodologies, flow customization/automation, synthesis, LEC, floor-planning, power/clock distribution, IP block assembly, place & route, and timing closure.
- Implement top-level partitioning, chip integration, and assemble.
- Work with packaging, power-grid designer to plan on bumps, power-grid distribution for multiple domains at the chip-level.
- Implement chip-level routing, power-planning, and timing closure.
- Perform power and noise analysis, RC extraction, LEC and physical verification at the block and chip-level.
Required Skills and Experience
- 2+ years of hand-on physical design experience from netlist to GDS on sub-micron node 90nm or lower
- Hand-on experience with Cadence or Synopsys physical implementation tool and Calibre DRC/LVS physical verification tool
- Experience with floor-plan trade off, placement and routing approaches, pre- and post-silicon ECO, timing closure, congestion resolution, IR-drop and crosstalk reduction techniques.
- Experience with high-speed Clock Tree Synthesis, topology and trade off
- Experience with signal integrity effect and solution
- Experience with constraint debug, timing closure are plus
- Experience with FinFET technology is a plus
- Good communication and teamwork skills
- Good English communications skills, both verbal and writing
- Familiarity with ARM/RISC-V SoC CPU architectures and peripheral interconnects
- Familiarity with different IP implementations such as ROM, RAM, FLASH, I2C, SPI, UART or other IPs.
- Scoping of design validation and verification requirements
- General knowledge of CPU operations and Software toolchains
- Desirable to have experience in signal processing for RF transceivers (NFC, Bluetooth), and high-speed ADCs.
- BS/MS/Ph.D in Electronic/Physic/Computer Engineering/Computer Science or a related field.