About Us
Nanochap is a young fabless semiconductor company headquartered in Hangzhou with the core R&D team in Melbourne, Australia. We specialise in neural interface and biosensing SoCs. The company is committed to the R&D, design, packaging, testing, and commercialisation of ultra-high density neural interface chips, biosensing chips, and other medical device related chips. Nanochap is expanding and we are looking for talents in but not limited to Analog Design, Analog Layout, RTL Design, Physical Design to join our newly opened office in Ho Chi Minh city.
Job Responsibilities
- Work on custom layout Analog IPs like LDO, PLL, DLL, Bandgap, PMIC, Clock trees…
- Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
- Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield.
- Participate in building and enhancing layout flow for faster, higher quality design process.
- Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
- Do PERC verification for ESD/LUP checks
- Complete all design quality checks and data quality checks
- Work with Place and Route engineer to integrate analog layouts into top level.
- Do design reviews across global team
- May collaborate in package design (interposer design, RDL design)
- Work closely with design team in Viet Nam and global to ensure the success of the whole product.
Required Skills and Experience
- Understand MOSFET fundamentals and passionate about IC design
- Good English communication
- Good team player
- Self-motivated
- Is a plus:
- 2+ years of experience with Custom Layout job
- Familiar with Layout entry tools: Cadence, Synopsys is a plus
- Familiar with Layout verification tools: Mentor Calibre, Synopsys ICV is a plus
- Understand basic semiconductor fabrication processes is a plus
- Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR.
- Experienced with writing layout review presentations and layout verification reports
Desirable:
- Familiarity with ARM/RISC-V SoC CPU architectures and peripheral interconnects
- Familiarity with different IP implementations such as ROM, RAM, FLASH, I2C, SPI, UART or other IPs.
- Scoping of design validation and verification requirements
- General knowledge of CPU operations and Software toolchains
- Desirable to have experience in signal processing for RF transceivers (NFC, Bluetooth), and high-speed ADCs.
Education:
- BS/MS/Ph.D in Electronic/Physic/Computer Engineering/Computer Science or a related field.
