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Design & Verification Engineer at CME Japan 230 views

Job Description

  • Member : 5 members
  • Experience : 2-3 year or more
  • Age : No limit
  • Position : Project leader/Project member
  • Recruitment time: After April 2022
  • Working location : Japan (CMEJ or Customer site)
  • Condition : After being hired by CMEV, education is conducted for 3 months, and then transferred to CMEJ (minimum 1 year).
  • Specific business content:


  • Very good benefit for employee and your family
  • Be ready to relocate in Japan

Job Requirements

Is the specification required by the customer, and specific design verification work is carried out using the following languages.


    • Functional specifications (English)
    • Implementation specifications (English)
    • RTL (Verilog/SystemVerilog)
    • Verification strategy (English)
    • Verification item table (English)
    • Verification environment construction/verification scenario (SystemVerilog/SVA/UVM/C)
    • Verification environment manual (English)
    • Verification result report (English)

We want this candidate to win the trust of customers, bring back customer projects to Vietnam, carry out projects as a team leader, and play an active role. Or, after returning to Vietnam, I would like this candidate to participate in CMEV projects and play an active role as a team leader with the aim of further improving several kind of skills.


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CM Engineering Vietnam is a global semiconductor companies

LSI Functional Verification Service

The keys to functional verification are “verification strategy” and “highly complete verification item extraction.”

Our functional verification services emphasize highly complete verification item extraction while also generating test benches and functional scenarios, random verification, and even functional coverage to meet customer demands by providing these services from a wide variety of angles. By implementing functional verification on the RTL and C models designed by customers from a third-party perspective, we improve quality of customers’ circuits.

FPGA Service

In recent years there has been remarkable progress on FPGA, and with the large scale number of gates on mass-produced types. The lengthening of evaluation and verification times to activate the normal operation of FPGA is seen as problematic and has become a serious obstacle for time to market in product development.

In our FPGA design quality improvement services, we consider a variety of aspects of FPGA development, including automatic RTL generation from specifications, verification item extraction and simulation, performance assessment, CDC verification of asynchronous circuits, and streamlining debug of firmware using verification platforms.



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